1. Field of the Invention
The present invention relates to a DC/DC converter.
2. Description of the Related Art
Electronic devices such as personal computers, dedicated game consoles, etc., employ a DC/DC converter (switching regulator) configured to step down a DC voltage having a given level to an optimum level for a load. FIG. 1 is a circuit diagram which shows a configuration of a DC/DC converter investigated by the present inventors.
A DC/DC converter 10r receives a DC input voltage VIN via its input line LIN, steps down the DC input voltage VIN thus received so as to stabilize its level to a predetermined target level, and supplies the DC voltage thus stepped down to a load (not shown) connected to an output line LOUT. The DC/DC converter 10 includes a switching transistor M1, a synchronous rectification transistor M2, an inductor L1, an output capacitor C1, a current sensing resistor RCS, and a control IC (Integrated Circuit) 100r. 
The switching transistor M1 and the synchronous rectification transistor M2 are each configured as an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and are sequentially arranged in series between the input line LIN and a ground line LGND. A connection node that connects the switching transistor M1 and the synchronous rectification transistor M2 will be referred to as “switching node N1”. The inductor L1 and the sensing resistor RCS are arranged in series between the switching node N1 and the output line LOUT. The output capacitor C1 is arranged between the output line LOUT and the ground line LGND. An input capacitor C2 is arranged between the input line LIN and the ground line LGND.
An upper gate (UGATE) terminal and a lower gate (LGATE) terminal are connected to the gate of the switching transistor M1 and the synchronous rectification transistor M2, respectively. A phase terminal (PHASE) is connected to the switching node N1. The output voltage VOUT is divided by resistors R1 and R2. A feedback voltage VFB, which is proportional to the output voltage VOUT, is input to a feedback terminal (FB) of the control IC 100. Current detection terminals (ISEN+ and ISEN−) are respectively connected to the respective terminals of the sensing resistor RCS. A bootstrap capacitor C3 is arranged between the switching node N1 and a boot terminal (BOOT).
The control IC 100r includes a pulse modulator 102, a high-side driver 104, a low-side driver 106, a current detection circuit 108, and a bootstrap switch SW1.
The pulse modulator 102 is configured to generate a pulse signal SPWM having a duty cycle adjusted such that the feedback voltage VFB matches a predetermined reference voltage. The pulse modulator 102 is configured as a known modulator, examples of which include a voltage mode modulator, a peak current mode modulator, an average current mode modulator, a fixed on-time mode modulator, a fixed off-time mode modulator, and a hysteresis control modulator. The high-side driver 104 and the low-side driver 106 are configured to perform switching of the switching transistor M1 and the synchronous rectification transistor M2 in a complementary manner according to the pulse signal SPWM. An upper power supply terminal of the high-side driver 104 is connected to the BOOT terminal, and a lower power supply terminal thereof is connected to the PHASE terminal.
In a case in which the switching transistor M1 is configured an N-channel MOSFET, in order to turn on the switching transistor M1, there is a need to input, to the gate of the switching transistor M1, a high-level voltage VH that is higher than the input voltage VIN. The bootstrap switch SW1 and the bootstrap capacitor C3 constitute a bootstrap circuit configured to generate a high-level voltage VH.
The bootstrap switch SW1 is arranged between a power supply line LVDD of the control IC 100r and the BOOT terminal. The bootstrap switch SW1 is configured as a transistor or a diode. When the switching transistor M1 is off and the synchronous rectification transistor M2 is off, the bootstrap switch SW1 is turned on. When the switching transistor M1 is off and the synchronous rectification transistor M2 is on, the bootstrap switch SW1 is turned on.
When the switching transistor M1 is off, the synchronous rectification transistor M2 is on, and the bootstrap switch SW1 is on, the PHASE terminal is set to the ground voltage VGND, and the BOOT terminal is set to the power supply voltage VDD. In this state, the bootstrap capacitor C3 is charged by the power supply voltage VDD.
When the switching transistor M1 is on, the synchronous rectification transistor M2 is off, and the bootstrap switch SW1 is off, the PHASE terminal is set to the input voltage VIN. Accordingly, the high-level voltage VH that develops at the BOOT terminal is set to (VIN+VDD). The power supply voltage VDD is configured to be higher than the gate-source threshold voltage VTH of the switching transistor M1. Thus, when the high-side driver 104 supplies the high-level voltage VH=VIN+VDD to the gate of the switching transistor M1, the switching transistor M1 is turned on.
The current detection circuit 108 receives, as an input signal, a voltage drop (detection voltage) VS that develops at the sensing resistor RCS. The detection voltage VS is proportional to a coil current IL that flows through the inductor L1. The coil current IL flows in a pulse manner according to switching of the DC/DC converter 10. The load current IOUT is represented by the time average of the coil current IL. The current detection circuit 108 detects the coil current IL based upon the detection voltage VS. The coil current IL thus detected is used by the pulse modulator 102 to generate the pulse signal SPWM, or is used to perform overcurrent protection, and/or is stored in a register after being converted into a digital value. The current value thus stored in the register is used as a reference value by other ICs.